Conductive lines are used in integrated circuitry as electrical interconnects. Aluminum has historically been the dominant interconnect material, but is being replaced by copper in part due to its lower electrical resistance and higher electromigration resistance. Using a lower resistivity interconnect material like copper decreases the interconnect RC delay, which increases the speed of the circuit.
The copper-comprising material of conductive lines may be deposited by a number of methods, for example, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and electrochemical deposition. Electrochemical deposition is becoming the most popular method due its low costs and superior fill capability. A plurality of integrated circuits is typically fabricated relative to a single semiconductor substrate/wafer at the same time, with the substrate subsequently being cut into individual chips or die. It is of course desirable that the various layers which are deposited across the substrate be of uniform thickness independent of location on the substrate.
In electrochemical deposition, a substrate having a conductive surface is immersed in a solution containing metal ions. The conductive surface is electrically connected to a power supply that passes current through the surface and to the solution. The metal ions within the solution will be deposited as metal onto the conductive surface. Accordingly, deposition of the desired material occurs selectively relative to conductive outermost surfaces of the substrate to which a voltage potential is applied. Typically, the electrical connection to the conductive material outer surface to produce the voltage potential is made at the edge of the substrate. Such can result in a voltage drop from the edge of the substrate to its center due to resistance in the conductive material being deposited upon. If sufficiently great, the voltage drop adversely impacts current density from the edge of the substrate to the center of the substrate, and produces thinner or no deposited film thickness at the center compared to the edge of the substrate. This is commonly referred to as “terminal effect”, which undesirably may result in thickness of the finished layer varying from the center of the substrate to the edge of the substrate. As device feature size continues to scale down, the conductive barrier and seed layers reduce in thickness. This leads to high resistance that may cause severe terminal effect.
There are a number of hardware and process approaches that may be used to reduce or diminish the terminal effect. Such include increasing the resistivity of the electrochemical bath, insertion of a highly resistive membrane adjacent to the wafer surface, and use of concentrically placed multiple or segmented anodes with different voltages being applied thereto. Additionally or alternately, insulating shielding might be provided in the bath around the edge of the wafer, and additional cathodes might be used to divert current from the edge of the wafer.
Regardless, in the finished integrated circuit construction, conductive interconnecting lines are spaced and separated from one another by dielectric material. Such inherently results in undesired parasitic capacitance which may be reduced by using low dielectric constant (low-k) material to reduce undesired parasitic capacitance.
While the invention was motivated in addressing the above-identified issues, the invention is in no way so limited.